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november 2016 docid026591 rev 6 1 / 24 this is information on a product in full production. www.st.com stgib15ch60ts - l sllimm? - 2nd series ipm, 3 - phase inverter, 20 a, 600 v short - circuit rugged igbt datasheet - production data features ? ipm 20 a, 600 v 3 - phase igbt inverter bridge including 2 control ics for gate driving and freewheeling diodes ? 3.3 v, 5 v ttl/cmos inputs with hysteresis ? internal bootstrap diode ? undervoltage lockout of gate drivers ? smart shutdown function ? short - circuit protection ? shutdown input/fault output ? separate open emitter outputs ? built - in temperature sensor ? comparator for fault protection ? short - circuit rugged tfs igbts ? very fast, soft recovery diodes ? 85 k ntc ul 1434 ca 4 recognized ? fully isolated package ? 1500 vrms/min. isolation ratings applications ? 3 - phase inverters for motor drives ? home appliances such as: washing machines, refrigerators, air conditioners and sewing machine description this second series of sllimm (small low - loss intelligent molded module) provides a compact, high performance ac motor drive in a simple, rugged desig n. it combines new st proprietary control ics (one ls and one hs driver) with an improved short - circuit rugged trench gate field - stop (tfs) igbt, making it ideal for 3 - phase inverter systems such as home appliances and air conditioners. sllimm? is a tradem ark of stmicroelectronics. table 1: device summary order code marking package packing stgib15ch60ts - l gib15ch60ts - l sdip2b - 26l type l tube
contents stgib15ch60ts - l 2 / 24 docid026591 rev 6 contents 1 internal schematic diagram and pin configuration ....................... 3 2 absolute maximum ratings ................................ ............................. 5 2.1 thermal data ................................ ................................ ..................... 5 3 electrical characteristics ................................ ................................ 6 3.1 inverter part ................................ ................................ ....................... 6 3.2 control / protection part ................................ ................................ ..... 7 4 fault management ................................ ................................ ......... 10 4.1 tso output ................................ ................................ ...................... 11 4.2 smart shutdown function ................................ ................................ . 11 5 application circuit exa mple ................................ .......................... 14 5.1 guidelines ................................ ................................ ....................... 15 6 ntc thermistor ................................ ................................ .............. 17 7 electrical characteristics (curves) ................................ ................ 19 8 package infor mation ................................ ................................ ..... 21 8.1 sdip2b - 26l type l package information ................................ ........ 21 9 revision history ................................ ................................ ............ 23
stgib15ch60ts - l internal schematic diagram and pin configuration docid026591 rev 6 3 / 24 1 internal schematic diagram and pin configuration figure 1 : internal schematic diagram and pin configuration
internal schematic diagram and pin configuration stgib15ch60ts - l 4 / 24 docid026591 rev 6 table 2: pin description pin symbol description 1 nc - 2 vbootu bootstrap voltage for u phase 3 vbootv bootstrap voltage for v phase 4 vbootw bootstrap voltage for w phase 5 hinu high - side logic input for u phase 6 hinv high - side logic input for v phase 7 hinw high - side logic input for w phase 8 vcch high - side low voltage power supply 9 gnd ground 10 linu low - side logic input for u phase 11 linv low - side logic input for v phase 12 linw low - side logic input for w phase 13 vccl low - side low voltage power supply 14 sd /od shutdown logic input (active low) / open - drain (comparator output) 15 cin comparator input 16 gnd ground 17 tso temperature sensor output 18 nw negative dc input for w phase 19 nv negative dc input for v phase 20 nu negative dc input for u phase 21 w w phase output 22 v v phase output 23 u u phase output 24 p positive dc input 25 t2 ntc thermistor terminal 2 26 t1 ntc thermistor terminal 1
stgib15ch60ts - l absolute m aximum ratings docid026591 rev 6 5 / 24 2 absolute maximum ratings t j = 25 c unless otherwise specified table 3: inverter part symbol parameter value unit v pn supply voltage among p - n u , - n v , - n w 450 v v pn(surge) supply voltage surge among p - n u , - n v , - n w 500 v v ces collector - emitter voltage each igbt 600 v i c continuous collector current each igbt (t c = 25 c) 20 a continuous collector current each igbt (t c = 80 c) 15 i cp peak collector current each igbt (less than 1 ms) 40 a p tot total dissipation at t c = 25 c each igbt 81 w t scw short - circuit withstand time, v ce = 300 v, t j = 125 c, v cc = v boot = 15 v, v in = 0 to 5 v 5 s table 4: control part symbol parameter min. max. unit v cc supply voltage between v cch - gnd, v ccl - gnd - 0.3 20 v v boot bootstrap voltage - 0.3 619 v v out output voltage among u, v, w and gnd v boot - 21 v boot + 0.3 v v cin comparator input voltage - 0.3 20 v v in logic input voltage applied among hinx, linx and gnd - 0.3 15 v v sd od ? open - drain voltage - 0.3 7 v i sd od ? open - drain sink current 10 ma v tso temperature sensor output voltage - 0.3 5.5 v i tso temperature sensor output current 7 ma table 5: total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 s) 1500 v t j power chip operating junction temperature range - 40 to 175 c t c module operation case temperature range - 40 to 125 c 2.1 thermal data table 6: thermal data symbol parameter value unit r th(j - c) thermal resistance junction - case single igbt 1.85 c/w thermal resistance junction - case single diode 2.8
electrical characteristics stgib15ch60ts - l 6 / 24 docid026591 rev 6 3 electrical characteristics t j = 25 c unless otherwise specified 3.1 inverter part table 7: static symbol parameter test conditions min. typ. max. unit i ces collector - cut off current v ce = 600 v, v cc = v boot = 15 v - 100 a v ce(sat) collector - emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 to 5 v, i c = 15 a - 1.55 2.1 v v cc = v boot = 15 v, v in = 0 to 5 v, i c = 20 a - 1.65 v f diode forward voltage v in = 0, i c = 15 a - 1.54 2.15 v v in = 0, i c = 20 a - 1.65 v notes: (1) applied among hinx, linx and gnd for x = u, v, w. table 8: inductive load switching time and energy symbol parameter test conditions min. typ. max. unit t on (1) turn - on time v dd = 300 v, v cc = v boot = 15 v, v in (2) = 0 to 5 v, i c = 15 a - 320 - ns t c(on) (1) crossover time on - 160 - t off (1) turn - off time - 510 - t c(off) (1) cross over time off - 102 - t rr reverse recovery time - 290 - e on turn - on switching energy - 440 - j e off turn - off switching energy - 213 - e rr reverse recovery energy - 59 - t on (1) turn - on time v dd = 300 v, v cc = v boot = 15 v, v in (2) = 0 to 5 v, i c = 20 a - 338 - ns t c(on) (1) crossover time on - 178 - t off (1) turn - off time - 500 - t c(off) (1) crossover time off - 92 - t rr reverse recovery time - 300 - e on turn - on switching energy - 624 - j e off turn - off switching energy - 296 - e rr reverse recovery energy - 80 - notes: (1) t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of the igbt itself under the internally given gate driving conditions. (2) applied among hinx, linx and gnd for x = u, v, w.
stgib15ch60ts - l electrical characteristics docid026591 rev 6 7 / 24 figure 2 : switching time test circuit figure 3 : switching time definition 3.2 control / protection part table 9: high and low - side drivers symbol parameter test conditions min. typ. max. unit v il low logic level voltage 0.8 v v ih high logic level voltage 2 v
electrical characteristics stgib15ch60ts - l 8 / 24 docid026591 rev 6 symbol parameter test conditions min. typ. max. unit i inh in logic 1 input bias current in x =15 v 80 150 200 a i ini in logic 0 input bias current in x =0 v 1 a high - side v cc_hys v cc uv hysteresis 1.2 1.4 1.7 v v cc_th(on) v cch uv turn - on threshold 11 11.5 12 v v cc_th(off) v cc uv turn - off threshold 9.6 10.1 10.6 v v bs_hys v bs uv hysteresis 0.5 1 1.6 v v bs_th(on) v bs uv turn - on threshold 10.1 11 11.9 v v bs_th(off) v bs uv turn - off threshold 9.1 10 10.9 v i qbsu undervoltage v bs quiescent current v bs = 9 v, hinx (1) = 5 v 55 75 a i qbs v bs quiescent current v cc = 15 v, hinx (1) = 5 v 125 170 a i qccu undervoltage quiescent supply current v cc = 9 v, hinx (1) = 0 v 190 250 a i qcc quiescent current v cc = 15 v, hinx (1) = 0 v 560 730 a r ds(on) bs driver on - resistance 150 low - side v cc_hys v cc uv hysteresis 1.1 1.4 1.6 v v ccl_th(on) vccl uv turn - on threshold 10.4 11.6 12.4 v v ccl_th(off) vccl uv turn - off threshold 9.0 10.3 11 v i qccu undervoltage quiescent supply current v cc = 10 v, sd ? ? ? ? pulled to 5 v through r sd = 10 k, cin = linx (1) = 0 600 800 a i qcc quiescent current v cc = 15 v, sd ? ? ? ? = 5 v, cin = linx (1) = 0 700 900 a v ssd smart sd ? ? ? ? unlatch threshold 0.5 0.6 0.75 v i sdh sd ? ? ? ? logic 1 input bias current sd ? ? ? ? = 5 v 25 50 70 a i sdi sd ? ? ? ? logic 0 input bias current sd ? ? ? ? = 0 v 1 a notes: (1) applied among hinx, linx and gnd for x = u, v, w
stgib15ch60ts - l electrical c haracteristics docid026591 rev 6 9 / 24 table 10: temperature sensor output symbol parameter test conditions min. typ. max. unit v tso temperature sensor output voltage t j = 25 c 0.974 1.16 1.345 v i tso_snk temperature sensor sink current capability 0.1 ma i tso_src temperature sensor source current capability 4 ma table 11: sense comparator (vcc = 15 v, unless otherwise is specified) symbol parameter test conditions min. typ. max. unit i cin cin input bias current v cin =1 v - 0.2 0.2 a v ref internal reference voltage 460 510 560 mv v od open - drain low level output voltage i od = 5 ma 500 mv t cin_sd c in comparator delay to sd ? ? ? ? sd ? ? ? ? pulled to 5 v through r sd =10 k; measured applying a voltage step 0 - 1 v to pin cin 50% cin to 90% sd ? ? ? ? 240 320 410 ns sr sd sd ? ? ? ? fall slew rate sd ? ? ? ? pulled to 5 v through r sd =10 k; cl=1 nf through sd ? ? ? ? and ground; 90% sd ? ? ? ? to 10% sd ? ? ? ? 2 5 v/s comparator is enabled even if v cc is in uvlo condition but higher than 4 v.
fault management stgib15ch60ts - l 10 / 24 docid026591 rev 6 4 fault management the device integrates an open - drain output connected to sd ? ? ? ? pin. as soon as a fault occurs the open - drain is activated and lvgx outputs are forced low. two types of fault can be pointed out: ? overcurrent (oc) sensed by the internal comparator (see further details in section 4.2: "sm art shutdown function" ) ? undervoltage on supply voltage (v cc ) each fault enables the sd ? ? ? ? open - drain for a different time; refer to the following table 12: "fault timing" table 12: fault timing symbol parameter event time sd o pen - drain enable time result oc overcurrent event 20 s 20 s 20 s oc time uvlo undervoltage lock - out event 50 s 50 s 50 s until the vcc_ls exceeds the vcc_ls uv turn - on threshold uvlo time actually, the device remains in a fault condition ( sd ? ? ? ? at low logic level and lvgx outputs disabled) for a time also depending on rc network connected to sd ? ? ? ? pin. the network generates a time contribute, which is added to the internal value. figure 4 : overcurrent timing (w ithout contribution of rc network on ?? ? ? ? ? ) gipg120520141638fsr
stgib15ch60ts - l fault management docid026591 rev 6 11 / 24 figure 5 : uvlo timing (without contribution of rc network on ?? ? ? ? ? ) 4.1 tso output the device integrates the temperature sensor. a voltage proportional to the die temperature is available on tso pin. when this function is not used this pin can be left floating. 4.2 smart shutdown function the device integrates a comparator committed to the fault sensing function. the comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. the output signal of the c omparator is fed to an integrated mosfet with the open - drain output available on sd ? ? ? ? input. when the comparator triggers, the device is set in shutdown state and its outputs are all set to low level. gipg120520141644fsr
fault management stgib15ch60ts - l 12 / 24 docid026591 rev 6 figure 6 : smart shutdown timing waveforms in case of overcurrent event r on_od = v od /5 ma see table 11: "sense comparator (vcc = 15 v, unless otherwise is specified)" ; r pd_sd (typ.) = 5 v/i sdh
stgib15ch60ts - l fault management docid026591 rev 6 13 / 24 in common overcurrent protection architectures, the comparator output is usually connected to the sd ? ? ? ? input and an rc network is connected to this sd ? ? ? ? line so to create a monostable circuit which implements a protection time following to the fault condition. differently from the common fault detection systems, the device smart shutdown architecture allows the output gate driver to be immediately turned - off in case of fault, by minimizing the propagation delay between the fault detection event and the output switch - off. in fact, the time delay between the fault and the output turn - off is no more dependent o n the rc value of the external network connected to the pin. in the smart shutdown circuitry, the fault signal has a preferential path which directly switc hes off the outputs after the comparator triggering. at the same time the internal logic turns on the open - drain output and holds it on until the sd ? ? ? ? voltage goes below the v ssd threshold and toc time is elapsed. the driver outputs restart following the input pins as soon as the voltage on the sd ? ? ? ? pin reaches the highest threshold of this sd ? ? ? ? logic input. the smart shutdown system allows the time constant (that is the disable time after the fault event) of the exter nal rc network to be increased up to very wide values without increasing the delay time of the protection.
applicati on circuit example stgib15ch60ts - l 14 / 24 docid026591 rev 6 5 application circuit example figure 7 : application circuit example application designers are free to use a different scheme according to the specifications of the device. vtso/ntc fault lin w lin v lin u hin w hin v hin u vtso/ntc c 3 c 3 c 3 cbootw cboot v cbootu r 1 r 1 r 1 c 1 c 1 c 1 r 1 r 1 r 1 c 1 c 1 c 1 (1)nc (2)vbootu (3)vbootv (4)vbootw (5)hinu (6)hinv (7)hinw (8)vcch (9)gnd c 2 c 2 vcc vc c cvc c cvcc cts o cs d rs d microcontroller pwr_gnd to mcu/op-amp cs f rs f rshunt c 4 cvdc m (10)linu ( 1 1)linv (12)linw (13)vcc l (14)sd/od (15)cin (16)gnd (17)tso nw(18 ) nv(19) nu(20) w(21) v(22) u(23) p(24) t2(25) t1(26) l-side h-side c t o rt o 3.3v/5 v vtso/ntc dz1 dz1 dz1 dz2 dz2 3.3v/5 v sgn_gn d + - + - + -
stgib15ch60ts - l application circuit example docid026591 rev 6 15 / 24 5.1 guidelines 1. input signal s hin, lin are active high logic. a 100 k (typ.) pull - down resistor is built - in for each input pin. to avoid input signal oscillations, the wiring of each input should be as short as possible and the use of rc filters (r1, c1) on each input signal is sugg ested. the filters should be with a constant time of about 100 ns and placed as close as possible to the ipm input pins. 2. the use of a bypass capacitor c vcc (aluminum or tantalum) can reduce the transient circuit demand on the power supply. besides, to redu ce high frequency switching noise distributed on the power lines, a decoupling capacitor c 2 (100 to 220 nf, with low esr and low esl) should be placed as close as possible to each v cc pin and in parallel with the bypass capacitor. 3. t he use of the rc filter (rsf, csf) prevent s protection circuit malfunction . the constant time (rsf x csf) should be set to 1 s and the filter must be placed as close as possible to the cin pin. 4. the sd ? ? ? ? is an input/output pin (open - drain type if it is used as output). it should b e pulled up to a power supply (i.e., mcu bias at 3.3/5 v) by a resistor value that is able to keep the i od no higher than 5 ma (v od 500 mv when open - drain mosfet is on). the filter on sd ? ? ? ? should be sized to get a desired restarting time after a fault even t and placed as close as possible to the sd ? ? ? ? pin. 5. a decoupling capacitor c tso between 1 nf and 10 nf can be used to increase the noise immunity of the tso thermal sensor; a similar decoupling capacitor c ot (between 10 nf and 100 nf) can be implemented if t he ntc thermistor is available and used. in both cases, their effectiveness is improved if these capacitors are placed close to the mcu. 6. the decoupling capacitor c 3 (100 to 220 nf with low esr and low esl) in parallel with each c boot filters high frequency disturbances. both c boot and c 3 (if present) should be placed as close as possible to the u,v,w and v boot pins. bootstrap negative electrodes should be connected to u, v, w terminals directly and separated from the main output wires. 7. to prevent overvolta ge on the v cc pin, a zener diode (dz1) can be used. similarly on the v boot pin, a zener diode(dz2) can be placed in parallel with each c boot . 8. the use of the decoupling capacitor c 4 (100 to 220 nf, with low esr and low esl) in parallel with the electrolytic capacitor c vdc prevents surge destruction. both capacitors c 4 and c vdc should be placed as close as possible to the ipm (c 4 has priority over c vdc ). 9. by integrating an application - specific type hvic inside the module, direct coupling to the mcu terminals without an optocoupler is possible. 10. low inductance shunt resistors should be used for phase leg current sensing. 11. in order to avoid malfunctions, the wiring on n pins, the shunt r esistor and pwr_gnd should be as short as possible. 12. the connection of sgn_gnd to pwr_gnd on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. these guidelines ensure the specifications of the device for application designs. for further details, please refer to the relevant application note.
application circuit example stgib15ch60ts - l 16 / 24 docid026591 rev 6 table 13: recommended operating conditions symbol parameter test conditions min. typ. max. unit v pn su pply voltage applied among p - nu, n v , n w 300 400 v v cc control supply voltage applied to v cc - gnd 13.5 15 18 v v bs high - side bias voltage applied to v booti - out i for i = u, v, w 13 18 v t dead blanking time to prevent arm - short for each input signal 1.0 s f pwm pwm input signal - 40 c < t c < 100 c - 40 c < t j < 125 c 20 khz t c case operation temperature 100 c
stgib15ch60ts - l ntc thermistor docid026591 rev 6 17 / 24 6 ntc thermistor table 14: ntc thermistor symbol parameter test conditions min. typ. max. unit r 25 resistance t = 25 c 85 - k? r 125 resistance t = 125 c 2.6 - k? b b - constant t = 25 to 100 c 4092 - k t operating temperature range - 40 125 c figure 8 : ntc resistance vs. temperature 0 5 0 0 1 0 00 1 5 00 2 0 00 2 5 00 3 0 00 - 50 - 25 0 25 50 75 1 0 0 1 2 5 ( k ( c) gipg120520142249fsr
ntc thermistor stgib15ch60ts - l 18 / 24 docid026591 rev 6 figure 9 : ntc resistance vs. temperature - zoom 0 5 10 15 20 25 30 50 60 70 80 90 1 0 0 1 1 0 1 2 0 ( k) ( c) m i n m a x t y p gipg120520141304fsr
stgib15ch60ts - l electrical characteristics (curves) docid026591 rev 6 19 / 24 7 electrical characteristics (curves) figure 10 : output characteristics figure 11 : v ce(sat) vs. collector current figure 12 : diode v f vs. forward current figure 13 : e on switching energy vs. collector current
electrical characteristics (curves) stgib15ch60ts - l 20 / 24 docid026591 rev 6 figure 14 : e off switching energy vs. collector current figure 15 : v tso output characteristics vs. lvic temperature figure 16 : thermal impedance for the sdip2b - 26l igbt 10 -1 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 k gipd290720151032fsr t p (s)
stgib15ch60ts - l package information docid026591 rev 6 21 / 24 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 8.1 sdip2b - 26l type l package information figure 17 : sdip2b - 26l type l package outline 8450802_3_type_ l
packa ge information stgib15ch60ts - l 22 / 24 docid026591 rev 6 table 15: sdip2b - 26l type l package mechanical data (dimensions are in mm) ref. dimensions a 38.00 0.50 a1 1.22 0.25 a2 1.22 0.25 a3 35.00 0.30 c 1.50 0.05 b 24.00 0.50 b1 12.00 b2 14.40 0.50 b3 29.40 0.50 c 3.50 0.20 c1 5.50 0.50 c2 14.00 0.50 e 3.556 0.200 e1 1.778 0.200 e2 7.62 0.20 e3 5.08 0.20 e4 2.54 0.20 d 28.95 0.50 d1 3.025 0.300 e 12.40 0.50 e1 3.75 0.30 e2 1.80 f 0.60 0.15 f1 0.50 0.15 f 2.10 0.15 f1 1.10 0.15 r 1.60 0.20 t 0.400 0.025 v 0 / 5
stgib15ch60ts - l revision history docid026591 rev 6 23 / 24 9 revision history table 16: document revision history date revision changes 23 - jun - 2014 1 initial release. 27 - aug - 2014 2 updated table 1: device summary. 06 - aug - 2015 3 text and formatting changes throughout document. updated cover page title and features. updated section 2: absolute maximum ratings . updated section 3: electrical characteristics . updated section 6: recommendations . added section 8: electrical characterist ics (curves) . 09 - sep - 2015 4 modified: features modified: figure 1, 6 and 7 datasheet promoted to preliminary data to production data minor text changes 12 - oct - 2016 5 modified table 7: "static" , table 9: " high and low side drivers" and table 11: "sense c omparator (vcc = 15 v, unless otherwise is specified)" modified section 5.1: "guidelines" modified figure 11: "vce(sat) vs. collector current" , figure 12: "diode vf vs. forward current" and figure 15: "vtso output characteristics vs. lvic temperature" upda ted section 8.1: "sdip2b - 26l type l package information" minor text changes 18 - nov - 2016 6 updated table 7: "static" .
stgib15ch60ts - l 24 / 24 docid026591 rev 6 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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